This invention relates to controlling the clock output of a digital phase-locked loop (PLL) in order to minimize the phase and the frequency disturbances resulting from input source switchover.
A standard phase-locked loop (PLL) circuit generally functions to lock its output clock so as to coincide in time with an input reference signal clock. Typically, a phase difference between the two clocks of zero degrees is the design target. PLL circuits can be implemented in either predominately digital or analog fashion, where the primary difference is in the way the output clock function is constructed. The analog PLL may, for example, employ a voltage-controlled oscillator (VCO), while a digital PLL may employ a digital accumulator circuit where the most significant bit (MSB) is typically used to form the output clock. Regardless of the specific type of PLL circuit, difficulties can arise when the system must switch over and select between more than one input reference signal. This requirement is common in modern telecommunications networks where different switches and routers may operate under different clock regimes. As packets, for example, are passed from one router to the next, the synchronizing clock of the first router may also be passed to the second router for data or flow control purposes.
The local PLL circuits must be equipped to handle the input reference signal switchover, where the signals may differ in frequency, phase, or both. It is common to have only phase variations between the old and the new reference signals, but it remains difficult to maintain the clock output because it must shift so as to align, or coincide in time, with the new input reference signal. The problem appears as a phase jump or as a disturbance on the output of the PLL, which is an undesirable aspect in many applications.
Now, a solution that is known in the art pertaining to analog PLL systems will be described.
Particularly for analog PLL systems, a programmable delay line can be used to minimize the clock output phase disturbance. When an input reference signal switchover occurs, a delayed version of the PLL output clock is extracted at a point where the output signal phase is about equivalent to the phase of the new reference signal. This delayed PLL output clock version is then used as the feedback signal essential to close the control loop.
FIG. 1 is a diagram representative of this approach, indicated by the general reference character 100. The reference signals, C1 and C2, connect to a first multiplexer circuit 102 and also to the phase difference measurement logic and control block 120. The output of first multiplexer 102 connects as the first input to the phase and frequency detection block 104. The output of block 104 serves as the input to the loop filter/oscillator block 106. The output of block 106 connects as the input to the clock delay line 108. The individual delay stage outputs 112-0 to 112-n are inputs to a second multiplexer 114. Also, the clock output signal 110 is derived from an intermediate delay line point. The feedback signal 116 is the output of the second multiplexer 114 and it is also the second input to the phase and frequency detection block 104. Finally, the selection control 118 for the second multiplexer is generated by block 120.
The basic operation of the system 100 is well known and understood in the art. The essential features of this approach during the switchover of the input reference signals will now be described.
If the circuit is already phase-locked to reference signal C1, clock output 110 will effectively track this reference signal. One of the individual delay stage outputs 112-0 to 112-n will be selected via the selection control 118 so as to provide the appropriate feedback signal 116 so that there is phase alignment between the feedback signal and C1. This effectively implements a programmable delay line between the output of oscillator 106 and the feedback signal. When a reference signal switchover occurs, say, from reference signal C1 to reference signal C2, the selection control 118 changes so that a different selection of the delay stage outputs 112-0 to 112-n is made. Thus, the new programmable delay tap point is selected so that the phase of the clock output 110 about matches the phase of the new reference signal, C2.
The approach described above serves to minimize the phase adjustment and disturbance on the clock output during the described reference signal switchover; however, there are several limitations and disadvantages associated with this approach to the problem. First, because of reasonable physical circuit implementation limits, there is an effective limit to the total length of the delay elements that can be constructed (i.e., the silicon chip area implementation cost can be high). Second, the delay stage size, or the effective delay of each stage, sets an incremental limit on the overall programmable delay line. This can make it more difficult to phase match the new reference signal because the phase difference between the old and the new reference signals may fall within the delay of a given delay stage, possibly resulting in clock output disturbances upon reference signal switchover or difficulty in ultimately phase matching the clock output to the new reference signal. A way to address this issue could be to implement the delay line using delay stages of different delay values (i.e., delay granularities), but this leads to physical implementation and delay matching difficulties.
A third disadvantage of the approach described above is that most delay line implementations are highly susceptible to variations in operating temperature, power supply voltage levels, and manufacturing processes. These factors could manifest as clock output phase disturbances becoming apparent under certain operating conditions, but not others, for the same reference signal switchover situation and reference signal characteristics, as an example. A fourth concern relates to the finite range of the delay line. For large phase mismatches, it may not provide enough delay for phase matching. If the minimum delay stage increment is too large for a small phase difference, this can also be a problem for phase locking, depending on the phase difference tolerances of the system. Finally, the approach described above requires a relatively complex control system in order to fine tune the selection of the appropriate delay tap point.
It would be desirable to arrive at some way of providing clock output control during reference signal switchover that is less complicated, is more reliable over the expected operating conditions and process variations, and is generally more flexible than other conventional approaches.
A Phase Locked Loop (PLL) system employing a digital frequency synthesis technique is coupled to a pair of accumulators and associated control circuitry. The clock output signal is generated from the most significant bit (MSB) of the first accumulator output. The feedback signal is generated from the MSB of the second accumulator output. Based on master switchover control notification that an input reference switchover will occur, a transition edge detector/switchover controller block places the system in a hold mode. The transition edge detector/switchover controller also generates the multiplexer control signal and the reset control signal. The reset control signal initializes the state of the second accumulator based on a phase comparison between the old and the new reference signals. In this way, the feedback signal closely approximates the new reference signal. Finally, the system is fully switched over to accept the new reference signal through the multiplexer and the system is taken out of the hold mode.
An advantage of the invention is that the disturbance on the clock output during the reference signal switchover is minor.
Another advantage of the invention embodiment is that the system performance is largely independent of variations in operating temperature, supply voltage, or manufacturing process because of the digital nature of the design.
Another advantage of the invention is that there is no delay line limitation due to the digital accumulator structure driving the feedback loop.
Another advantage of the invention is that the system time resolution is limited by the local control clock rate, as opposed to an analog delay stage element.
Yet another advantage of the invention is that a relatively simple input phase measuring system can be employed to set the effective delay of the feedback signal.